One goal in the design of digital systems is to clock data and control signals through the system at high clock rates. The higher the clock rate, the faster the these signals move through the system. To achieve maximum system performance, it is necessary to maintain a precise timing relationship between the clock and data paths. In a latch, for example, the data must be present at the input before the latch is clocked. A delay element is used to introduce the appropriate delay into the clock path to produce the desired timing. Often, an adjustable delay element is preferred to optimize circuit parameters such as set-up or hold time for a latch or settling time for a digital-to-analog converter.
Prior adjustable delay elements have tended to exhibit a nonlinear response to the delay control and a limited adjustment range. For example, a delay element commonly used in ECL designs is based upon controlling the slew rate of the output emitter followers by adjusting the standing current in these emitter followers. This method has minimal adjustment range because only the negative-going edges are significantly affected by the standing current. In single-ended use, this delay element is nonsymmetrical, producing variable delay for the negative-going signals but essentially fixed delay for positive-going signals. In differential systems, very slow negative-going edges produce only small delay changes, and the delay generated is a nonlinear function of the control current.